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<head><meta charset="utf-8"><title>Big endian · project-inline-asm · Zulip Chat Archive</title></head>
<h2>Stream: <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/index.html">project-inline-asm</a></h2>
<h3>Topic: <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html">Big endian</a></h3>

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<a name="189126460"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189126460" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189126460">(Feb 26 2020 at 15:49)</a>:</h4>
<p>I think the current approach of accepting any type as long as it fits in the target register won't work on big endian.</p>



<a name="189126690"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189126690" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189126690">(Feb 26 2020 at 15:51)</a>:</h4>
<p>For example if you want to put an <code>i8</code> into a 128-bit SIMD register, you can either zero-extend to <code>i128</code> and transmute, or convert to <code>i8x1</code> and then zero-extend the vector to <code>i8x16</code>.</p>



<a name="189126723"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189126723" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189126723">(Feb 26 2020 at 15:52)</a>:</h4>
<p>On big-endian those two operations will yield different results.</p>



<a name="189126795"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189126795" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189126795">(Feb 26 2020 at 15:52)</a>:</h4>
<p>cc <span class="user-mention" data-user-id="239881">@Josh Triplett</span> since you were arguing for allowing <code>i128</code> operands for vector registers.</p>



<a name="189126892"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189126892" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189126892">(Feb 26 2020 at 15:53)</a>:</h4>
<p>IMO we have to go back to the old system where only certain types are allowed as asm operands, depending on the register class. (Rather than just checking the size)</p>



<a name="189127051"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189127051" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189127051">(Feb 26 2020 at 15:55)</a>:</h4>
<p>Registers don't normally have endianness, but vector registers are an interesting case...</p>



<a name="189127141"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189127141" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189127141">(Feb 26 2020 at 15:56)</a>:</h4>
<p>But I can't imagine treating an i8 as i8x1 and extending to i8x16.</p>



<a name="189127239"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189127239" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189127239">(Feb 26 2020 at 15:57)</a>:</h4>
<p>Trying to use an i8 where a larger register size is expected only makes sense as the equivalent of an "as" cast to me.</p>



<a name="189127274"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189127274" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189127274">(Feb 26 2020 at 15:57)</a>:</h4>
<p>(also, that would be a sign extend)</p>



<a name="189127363"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189127363" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189127363">(Feb 26 2020 at 15:58)</a>:</h4>
<p>All that said, I don't know that I would expect to be able to use an i8 as a 128-bit register directly. I expect that to work on a general purpose register because it may be already stored in one.</p>



<a name="189128408"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189128408" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189128408">(Feb 26 2020 at 16:07)</a>:</h4>
<p>Another example on AArch64. There are separate instructions for loading an <code>i64</code> and <code>i8x8</code> from memory, and they return different register contents on big endian from the same bytes in memory.</p>



<a name="189129946"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189129946" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189129946">(Feb 26 2020 at 16:22)</a>:</h4>
<p>Well then, time to redesign this shit again...</p>



<a name="189143475"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189143475" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189143475">(Feb 26 2020 at 18:34)</a>:</h4>
<p>I think we'd never want to convert to a vector "implicitly"</p>



<a name="189143516"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189143516" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189143516">(Feb 26 2020 at 18:34)</a>:</h4>
<p>But converting from i8 to an i64 register makes sense.</p>



<a name="189143538"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189143538" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189143538">(Feb 26 2020 at 18:34)</a>:</h4>
<p>It makes even more sense on x86 where it may already be in <code>al</code>.</p>



<a name="189145667"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189145667" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189145667">(Feb 26 2020 at 18:51)</a>:</h4>
<p>My current plan is to specify the contents of registers as if they loaded the input value using X instruction.</p>



<a name="189145757"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189145757" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189145757">(Feb 26 2020 at 18:52)</a>:</h4>
<p>So for example, on ARM vector would be as if loaded by the <code>LD1</code> instruction, which handles big-endian correctly.</p>



<a name="189145847"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189145847" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189145847">(Feb 26 2020 at 18:53)</a>:</h4>
<p>Or on x86 for <code>k[1-7]</code> registers, it is specified as if the value was loaded by <code>KMOVB</code>, <code>KMOVW</code>, <code>KMOVD</code>, <code>KMOVQ</code>.</p>



<a name="189147724"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189147724" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189147724">(Feb 26 2020 at 19:11)</a>:</h4>
<p>That sounds reasonable to me.</p>



<a name="189147799"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189147799" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189147799">(Feb 26 2020 at 19:12)</a>:</h4>
<p>But this means that loading <code>i8</code> into an SSE register is not allowed</p>



<a name="189147822"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189147822" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189147822">(Feb 26 2020 at 19:12)</a>:</h4>
<p>I can live with that.</p>



<a name="189147831"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189147831" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189147831">(Feb 26 2020 at 19:12)</a>:</h4>
<p>Because there is no instruction for that. There is only <code>movss</code> and <code>movsd</code> for <code>i32</code> and <code>i64</code></p>



<a name="189147840"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189147840" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189147840">(Feb 26 2020 at 19:12)</a>:</h4>
<p>I expect to be able to load an i8, i16, i32, or i64 into a general-purpose register.</p>



<a name="189147892"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189147892" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189147892">(Feb 26 2020 at 19:13)</a>:</h4>
<p>But I don't necessarily expect to be able to load an i8 <em>directly</em> into an SSE register.</p>



<a name="189147905"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189147905" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189147905">(Feb 26 2020 at 19:13)</a>:</h4>
<p>Sure, there are byte load, i16 load, etc instructions</p>



<a name="189147914"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189147914" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189147914">(Feb 26 2020 at 19:13)</a>:</h4>
<p>for general regs only</p>



<a name="189147921"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189147921" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189147921">(Feb 26 2020 at 19:13)</a>:</h4>
<p>Well, there's also <code>al</code>. ;)</p>



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<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189147990" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189147990">(Feb 26 2020 at 19:14)</a>:</h4>
<p>I'm using loading from memory for the spec, anything else is a compiler optimization</p>



<a name="189148001"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189148001" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189148001">(Feb 26 2020 at 19:14)</a>:</h4>
<p>Sure.</p>



<a name="189148006"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189148006" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189148006">(Feb 26 2020 at 19:14)</a>:</h4>
<p>Though...</p>



<a name="189148034"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189148034" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189148034">(Feb 26 2020 at 19:14)</a>:</h4>
<p>That still leaves the question of whether we can avoid doing a <code>movzx</code>.</p>



<a name="189148405"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189148405" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189148405">(Feb 26 2020 at 19:17)</a>:</h4>
<p>I would like to be able to say "that's already in <code>al</code>, and you asked for <code>in(reg)</code>, so here's <code>al</code>".</p>



<a name="189149683"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189149683" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189149683">(Feb 26 2020 at 19:28)</a>:</h4>
<p>Hmm good point. My specification does leave it somewhat ambiguous as to what value the upper bits will have.</p>



<a name="189149748"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189149748" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189149748">(Feb 26 2020 at 19:29)</a>:</h4>
<p>Strictly speaking a load instruction (on ARM) will zero out the upper bits. But we don't want that since that's a useless zero-extension</p>



<a name="189149798"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189149798" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189149798">(Feb 26 2020 at 19:29)</a>:</h4>
<p>/me goes back to poking at LLVM internals to figure out how this stuff works</p>



<a name="189150506"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189150506" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189150506">(Feb 26 2020 at 19:37)</a>:</h4>
<p>What I'd <em>like</em> to do is to detect the type you hand the <code>asm!</code> directive, provide the corresponding register size, and then rely on the asm string to do with that (potentially smaller) register what it wants. Someone can always <code>movzx</code> from a short register into a long one, if they need a full-width value.</p>



<a name="189150533"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189150533" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Lokathor <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189150533">(Feb 26 2020 at 19:37)</a>:</h4>
<p>Does the "load with zero extension" take more time than "load without zero extension"? All the bits effectively gets determined in parallel right? Since at that level it's electrical signals per wire and such.</p>



<a name="189150535"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189150535" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189150535">(Feb 26 2020 at 19:37)</a>:</h4>
<p>Note that that <em>isn't</em> giving people access to undefined bits, because being handed <code>al</code> does not entitle you to presume anything about the value of the upper 56 bits.</p>



<a name="189150557"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189150557" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189150557">(Feb 26 2020 at 19:38)</a>:</h4>
<p><span class="user-mention" data-user-id="224471">@Lokathor</span> <code>movzx</code> costs more than "do nothing, it's already in a register". ;)</p>



<a name="189150642"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189150642" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189150642">(Feb 26 2020 at 19:38)</a>:</h4>
<p>I think it's architecture-dependent whether <code>movzx</code> is more expensive than <code>mov</code>.</p>



<a name="189150703"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189150703" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189150703">(Feb 26 2020 at 19:39)</a>:</h4>
<p>On a modern processor, <code>movzx</code> shouldn't be any more expensive than <code>mov</code>, but it's still more expensive than doing nothing. ;)</p>



<a name="189151037"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189151037" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189151037">(Feb 26 2020 at 19:42)</a>:</h4>
<p>If you need zero-extension then you can always just <code>as u64</code>.</p>



<a name="189151150"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189151150" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Lokathor <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189151150">(Feb 26 2020 at 19:43)</a>:</h4>
<p>Ah, so we're comparing with doing nothing at all. Right</p>



<a name="189151231"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189151231" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189151231">(Feb 26 2020 at 19:44)</a>:</h4>
<p>Basically it comes from the calling convention: on most platforms if you pass an <code>i8</code> (or anything smaller than the register size), the upper bits are undefined.</p>



<a name="189152043"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189152043" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Lokathor <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189152043">(Feb 26 2020 at 19:52)</a>:</h4>
<p>For ASM stuff I've exclusively seen docs given in terms of old C code where (naturally) arguments are always just "int"</p>



<a name="189152251"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189152251" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189152251">(Feb 26 2020 at 19:55)</a>:</h4>
<p>Yea inline asm is not really specified properly at all.</p>



<a name="189155876"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189155876" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189155876">(Feb 26 2020 at 20:33)</a>:</h4>
<p><span class="user-mention silent" data-user-id="143274">Amanieu</span> <a href="#narrow/stream/216763-project-inline-asm/topic/Big.20endian/near/189151037" title="#narrow/stream/216763-project-inline-asm/topic/Big.20endian/near/189151037">said</a>:</p>
<blockquote>
<p>If you need zero-extension then you can always just <code>as u64</code>.</p>
</blockquote>
<p>Agreed completely. I think <code>in(reg) some_u8_value</code> should pass it in the low 8-bits of a general-purpose register, and <code>in(reg) some_u8_value as u64</code> can zero-extend, and those are all the options we need.</p>



<a name="189156237"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189156237" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189156237">(Feb 26 2020 at 20:36)</a>:</h4>
<p>The only architecture which does not specify the upper bits as undefined is RISCV.</p>



<a name="189156258"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189156258" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189156258">(Feb 26 2020 at 20:37)</a>:</h4>
<p>It's a bit weird in that if you pass a <code>f32</code> into inline asm, it gets NaN-boxed into an <code>f64</code>.</p>



<a name="189156418"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189156418" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189156418">(Feb 26 2020 at 20:39)</a>:</h4>
<p>... and since inline asm doesn't have a spec, I don't know whether this is intentional or if this is an accident of the upper bits being undefined.</p>



<a name="189156496"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/216763-project-inline-asm/topic/Big%20endian/near/189156496" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/216763-project-inline-asm/topic/Big.20endian.html#189156496">(Feb 26 2020 at 20:40)</a>:</h4>
<p>(RISC-V single-precision instructions require that the upper 32 bits of the 64-bit FP register are 0xffffffff, otherwise the result is NaN)</p>



<hr><p>Last updated: Aug 07 2021 at 22:04 UTC</p>
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